Packages provide the interconnect from a chip to a printed circuit board (PCB). The package also provides protection for the chip from the environment. The overall objective of the package design is to provide these features at the lowest possible manufacturing cost.
A common process employed in semiconductor packaging is wire bonding, wherein a fine wire is connected between semiconductor die pads and inner ends of package lead fingers.
In one packaging scheme, a semiconductor die is mounted within an opening in a package having external leads (or pins). Bond pads on the die are wired to terminals within the package, and a lid is mounted over the opening containing the die. This type of package is usually formed of ceramic, and is relatively expensive to manufacture.
Another technique for packaging integrated circuit devices is mounting the die to a die attach pad on a lead frame, connecting the die to various inner lead fingers of the lead frame, and encapsulating the die, either with epoxy or with a plastic molding compound. Plastic packages are preferred by most commercial users for their low cost and low weight. Plastic packaging is discussed in the main, hereinafter.
As chips become more complex, their packages require more pins (or external leads), and hence become larger in size. Transfer molding large plastic packages involves the transfer of large amounts of melted plastic, and the injection of the plastic can cause bond wires connecting the chip to the leadframe to move and short against each other (wire sweep). Also, because of the set cure characteristics of plastic molding compound, a large molded body has a tendency to warp, causing difficulties when packages are mounted to a PCB.
Molding the entire package body ("fully molded") usually requires that the leadframe has a "dambar", namely a continuous ring of metal surrounding the body that prevents the plastic from flowing out of the mold cavity between the external leads of the leadframe. The dambar then has to be removed to isolate individual leads before the package is usable. With high pin count packages, the leads are often delicate and spaced closely (fine pitch), resulting in the need for very fine precision tooling for the trimming operation. This type of tooling is also very expensive, which adds to the overall cost of packaging.
Molding of the plastic around the leadframe also causes some leakage of the plastic onto the leadframe (flashing). The flash then has to be removed in a separate de-flashing (dejunking) step.
Attention is directed to commonly-owned U.S. Pat. No. 5,051,813, entitled PLASTIC-PACKAGED SEMICONDUCTOR DEVICE HAVING LEAD SUPPORT AND ALIGNMENT STRUCTURE, which discloses plastic packaging with and without dambars, dejunking, etc.
In the main, hereinafter, molding where the mold gate is disposed at the parting plane of the two mold halves is discussed, as most pertinent to the present invention.
The following U.S. Patents are cited of general interest in the field of packaging (annotations in parentheses): U.S. Pat No. 3,405,441 (hermetic sealing process using glass and metal lid on a ceramic substrate); U.S. Pat. No. 3,909,838 (package formed by sealing two halves or pre-molded body around a molded pill package bonded to a leadframe); U.S. Pat. No. 4,143,456 (glob top sealing devices mounted on a substrate); U.S. Pat. No. 4,264,917 (silicon substrate with glob top encapsulation); U.S. Pat. No. 4,300,153 (TAB device with a substrate bonded to the bottom of the die; glob top encapsulation); U.S. Pat. No. 4,330,790 (tape-mounted device encapsulated using a metal carrier and epoxy); U.S. Pat. No. 4,363,076 (flat TAB assembly); U.S. Pat. No. 4,507,675 (molded heatsink package); U.S. Pat. No. 4,594,770 (bonding a metal cap and a plastic cap around a leadframe); U.S. Pat. No. 4,857,483 (mold gate is not located at the parting plane of the mold halves); U.S. Pat. No. 4,872,825 (encapsulation method using a lamination process instead of injection or transfer molding); U.S. Pat. No. 4,874,722 (pre-molded flatpack encapsulated with silicone gel; dambar required; not encapsulated by molding); U.S. Pat. No. 4,890,152 (molded pin grid array package; not a surface mount flatpack construction); U.S. Pat. No. 4,913,930 (coating and encapsulating a device in a reel-to-reel format); U.S. Pat. No. 4,955,132 (flip chip mounting to a substrate); U.S. Pat. No. 4,961,105 (die back metallization); U.S. Pat. No. 4,974,057 (die coated with resin and then molded); U.S. Pat. No. 4,975,765 (high density flatpack with edge connectors; not a molded package); U.S. Pat. No. 4,982,265 (stackable TAB); U.S. Pat. No. 4,984,059 (leadframe tips overlap the top of the die surface); U.S. Pat. No. 4,996,587 (thin,stackable package); and U.S. Pat. No. 5,025,114 (leadframe construction resulting in multilayer structure for plastic packages).
The functional demands placed on modern integrated circuits have resulted in an ever-increasing demand for input/output (I/O) connections to the die. Hundreds of I/O connections are not uncommon. Commonly-owned, co-pending U.S. patent application Ser. No. 07/916,328 ("CNS-DIES"), discussed below, discloses a method for increasing I/O connections for an integrated circuit (die) of a given area. There remains a similar problem with the number of connections required in the package mounting and connecting to the die. Generally, there is a one-to-one correspondence between the number of package connections and the number of bond pads on the die.
Thus, there is a need for semiconductor packaging techniques that can accommodate increased lead count, particularly suited to the dies discussed in the aforementioned U.S. patent application Ser. No. 07/916,328.
Generally, semiconductor packages are used for (1) enclosing (protecting) a semiconductor (IC) die in some kind of package body, and (2) providing external connections for connecting the packaged die to external systems. Packaging the integrated circuit, requires at a minimum, (1) a conductive layer having a plurality of conductive lines, and (2) a "die-receiving area." As is discussed in greater detail hereinbelow, the inner ends of the conductive lines define the die-receiving area.
Once the die is mounted in (on) the die-receiving area, bond pads located on the die will be connected, usually by wire bonding or tape automated bonding (TAB) to inner end portions of the conductive lines.
Generally speaking, there are four distinct techniques of packaging a semiconductor device, in any case said package having one or more layers of conductive lines (leads, traces, or the like) exiting the package for electrically connecting the packaged die to other components, whether by mounting directly to a printed circuit (mother) board or by plugging the packaged device into a socket which in turn is mounted to the mother board. These are:
(1) plastic molding; PA1 (2) ceramic packaging; PA1 (3) PCB-substrate type packaging; and PA1 (4) tape-based packaging. PA1 (1) equilateral triangular shaped dies providing 14% more I/O than a square die of the same size (area); PA1 (2) right isosceles triangular shaped dies providing 21% more I/O than a square die of the same size (area); PA1 (3) 30.degree.-60.degree.-90.degree. right triangular shaped dies providing 28% more I/O than a square die of the same size (area); PA1 (4) "Greatly Elongated Rectangular" shaped dies providing 16% more I/O than a square die of the same size (area); and PA1 (5) Parallelogram shaped dies providing 14% more I/O than a square die of the same size (area).
Plastic molding typically involves a relatively rigid lead frame, wherein the lead frame has a patterned layer of conductive leads (conductive lines), the inner ends of which define the die-receiving area. A die is mounted to a die paddle, within the die-receiving area, and is connected to inner end portions of the conductive leads. The die and inner portion of the lead frame are encapsulated by plastic molding compound. Outer end portions of the conductive leads extend outside of the molded plastic body.
Ceramic packaging typically involves one or more layers of conductive traces (conductive lines) applied on interleaved ceramic layers. Again, the die-receiving area is defined by the inner ends of the conductive traces. Outer layers are typically ceramic. The die is mounted in a cavity (either up or down), connected to inner ends of the traces, and the cavity is closed by a lid. Outer ends of the traces are connected, within the ceramic, to external pins or leads (for example) on the exterior of the ceramic package body.
PCB-substrate type packaging involves a patterned layer of conductive traces (conductive lines) on a printed circuit board (PCB) substrate, and the inner ends of the conductive traces define the die-receiving area. The die is mounted to the substrate, connected to the inner ends of the traces, and may be encapsulated by epoxy, plastic molding compound, or in any suitable manner. Outer ends of the traces are connected to external pins or leads (for example), in a manner similar to ceramic packaging.
Tape-based packing involves a relatively non-rigid foil of conductive leads (conductive lines), supported by a plastic layer, and the inner ends of the conductive traces define the die-receiving area. A die is mounted to the substrate formed by the layer of conductive leads and plastic, and is connected to the inner ends of the conductive leads. Outer ends of the leads are connected to (or form) external interconnects for the packaged die.
In any of these, or other, packaging techniques, a die connected to conductive lines and having some sort of support and/or package body is referred to as a "semiconductor device assembly".
FIGS. 4A and 4B show two similar prior art layers 400, 400' of pattered conductive lines, which are applicable to any of the aforementioned package types. A "die-receiving area" 410, 410' is defined by the inner ends 408, 408' of a plurality of conductive lines 406, 406'. A die 402, 402' is mounted in the die-receiving area 410, 410' and bond pads 412, 412' on the die are connected to the inner ends of the conductive lines. Two techniques for attaching a die to conductive lines are shown. In FIG. 4A, the die 402 is wire bonded to the conductive lines 406, as indicated by bond wires 414 extending between the bond pads 412 and the conductive lines 406. In FIG. 4B, the die 402' is connected to the conductive lines 406' by tape automated bonding (TAB) techniques (indicated by 414'). Both of these techniques are well known. Other techniques (not shown) of connecting a die to a pattern of conductive lines include flip-chip and the like.
Notably, as shown in FIGS. 4A and 4B, the die is square. The conductive lines extend (radiate) from the die-receiving area, outward from the die. Hence, a sub-plurality of conductive lines are disposed on each of the four sides of the die, their inner ends defining a square die-receiving area. Also shown, by way of example, in FIGS. 4A and 4B are die attach pads 404, 404', which are generally somewhat larger than the die and somewhat smaller than the die-receiving area.
The conductive lines (406 and 406') include, but are not limited to, lead frame leads, tape leads, and traces on a ceramic or PCB substrate. Ultimately, a package body (not shown) may be formed about the die and inner portions of the conductive lines, as discussed above.
As a practical matter, the number of conductive lines (406 and 406') is determined by the number of bond pads (412 and 412') located on a given die (402 and 402'). A problem with the prior art is insufficient number of conductive lines (406 and 406').
Commonly owned, co-pending application Ser. No. 07/916,328 provides a technique for increasing the number of I/O bond pads for a given die. Hence, it is desirable to provide an increased number of conductive lines, defining a die-receiving area and connecting to the die bond pads, hence increasing the number of I/O connections.
Therefore, problems with mounting a die within a prior art square die-receiving area is the limitation placed on the number of conductive lines (406 and 406') defining the prior art square die-receiving area (e.g., 410 and 410'). Prior art inner ends (408 and 408') of conductive lines (406 and 406') make up a square die-receiving area, hence, providing I/O connection limited to the periphery of the square. Moreover, the prior art square die-receiving area does not accommodate the increased number of I/O connection on a given die provided in commonly owned co-pending patent application Ser. No. 07/916,328. Hence, what is needed is (at least) a layer of conductive lines defining a die-receiving area that provides an increased number of conductive lines, thus increasing the number of I/O connections.